Then describes the 4 function modules in vhdl , the vhdl programs have passed compile and debug in maxplus ii , the results of function simulation and timing simulation all prove that the design is correct , at last , maxplus ii generates a netlist file which can be download into chip 然后使用vhdl硬件描述语言对四大功能模块进行描述,在maxplus环境下编译、调试通过,功能仿真和时序仿真结果证明设计正确,最后生成可下载的网表文件。
The main work includes the deep study of microprocessor theory , the system - level design of the soft core that is performed based on it , the system function definition and partition , the design of all the functional modules . after completing system - level and algorithm - level designs , the rtl implementations of each module are performed and the functional simulation and fpga verification are carried out on the rtl codes . at last , the rtl codes are synthesized with synopsys " design compiler and the gat - level netlist is gotten 具体工作包括对微处理器理论的深入研究,并在此基础上完成16位risc微处理器软核16rmpu的系统级设计,实现系统功能定义和系统划分;完成软核各个模块的算法级设计和rtl级设计,并对软核的rtl级代码进行仿真和fpga验证;对软核进行dc ( designcompiler )综合,生成后端布局布线所需要的网表文件,最终实现微处理器软核的设计。