system clocks造句
例句与造句
- if your system clock is set to the correct time, the detectors will be shown in proper relation to the stars . they move around the celestial sphere once in 24 hours
如果你的系统时间设置正确，屏保中的探测器与天体位置将与现实中的相符。如果你对着屏保看一天，它们也将在24小时内围绕天球旋转一圈。 - lastly, we use the high level synthesis tool synplify to test the validity of the improving mcu . according to the synthesis result, the system clock reached about 66mhz
最后,采用synplicity公司的高层综合工具synplify对所设计的mcu进行了综合,综合结果验证了改进型mcu满足了要求,工作频率达到66mhz。 - a simple java class, six lines of code that reports the server system clock, is made into a web service and published into the ibm uddi business test registry
我们将一个由六行代码构成的简单java类包装成一个web服务，然后将其发布到ibmuddi业务测试注册中心（businesstestregistry），这个类报告服务器的系统时钟。 - by synchronizing their program with the system clock on the server generating the pseudo-random number, they are able to reduce the number of possible combinations down to a number on the order of 200, 000 possibilities
分隔背后的基本思想是如果我们将系统分成尽可能多的独立单元，那么我们可以将对系统可能造成损害的量降到最低。 - the circuit mainly includes the system power, the system clock, the rs-485 interface, the key and the led display, the 4-20ma conditioning and a / d conversion, the watchdog and the low voltage detection and the external eeprom, the warning circuit
主要包括:电源和时钟模块、rs-485通信模块、按键和led数码管显示模块、4-20ma调理及a/d转换模块、看门狗/低压检测模块和报警模块等。 - It's difficult to find system clocks in a sentence. 用system clocks造句挺难的
- the methods used include sharing a global form instance with an intrinsic timer control on it, a global class instance that raises events in response to a system clock callback, and a collection-based method that fires secondary interface methods of each member in response to system clock callbacks
使用的方法有用一个定时器控件来共享一个全局窗体实例；一个可以响应系统时钟回调的全局类的实例；一种基于集合的方法，使用每个接口的间接接口方法来响应系统时钟回调。 - the methods used include sharing a global form instance with an intrinsic timer control on it, a global class instance that raises events in response to a system clock callback, and a collection-based method that fires secondary interface methods of each member in response to system clock callbacks
使用的方法有用一个定时器控件来共享一个全局窗体实例；一个可以响应系统时钟回调的全局类的实例；一种基于集合的方法，使用每个接口的间接接口方法来响应系统时钟回调。 - the work for this thesis is as follows : firstly, based on previous studies, this thesis puts forward the information synchronization theory of collaborative system in dvr, gives a synchronous control scheme, including information transmission delay, entity states dead reckoning, advanced information-getting schema and system clock synchronization . secondly, this thesis brings forward the measures to solve the information consistency and the real time for the response of sharing operation . thirdly, this thesis designs a parallel rendering model, realizing its task scheduling in the agent and the communication between client and server
本文的主要工作是：一、在基于以前大量的研究基础上，给出了分布式虚拟现实环境下的协作系统的同步控制策略，包括信息的传输延迟、实体状态估算、信息预取策略及系统全局时钟同步；二、提出了解决信息一致性问题及共享操作响应的实时性问题的措施；三、在协同设计系统的信息同步理论的基础上，给出了并行绘制模型的设计，实现其在agent下的任务调度及client与server之间的信息通讯；四、最后给出了一个客户端几何形体的显示及空间操作的实例。 - in the beginning, the whole design flow is introduced . in the system design, the arithemetic about the memory structure, the enumeration of transfer mode the realization of the control endpoints ., the non-control endpoints, the configuration finit state machine > the configuration rom, the interrupt request the function of resume and remote wake-up, the system clock and the five interfaces are achieved
首先介绍了该外围控制ip所采用的设计流程，接着阐述了系统级的设计，主要包括内存结构、传输模式检测、控制端点与非控制端点的实现、配置有限状态机、配置rom、中断请求、恢复挂起功能、系统时钟域与复位以及各种接口电路的设计。 - with vc-12 virtual concatenation, we can make efficient and flexible use of the bandwidth . sdram, as a mass storage medium, is applied also . in this design, i use hy57v643220ct-6, with 32bit data width, up to 166m system clock, as the buffer of vc-12 virtual concatenation alignment and ethernet data transmission
本论文设计系统中采用了现代的hy57v643220ct-6作为外部存储器，它的数据线是32位宽，保证了吞吐量，时钟可高达166m，保证了速度，用它实现了多个以太网发送端缓存和多路vc-12虚级联的对齐。 - analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm . the system use input clock as system clock and use parallel structure in system to provide flexible speed
采用适合fpga特点的溢出控制设计方法;改进传统的寄存器交换法re(registerexchange)的幸存路径管理设计方法;全系统采用输入数据的同步时钟作为系统时钟,系统内部采用全并行的方式,以提供灵活的速度。
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