The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66 % ) , but the fault coverage and time performance are lower than gate - level test generation 实验数据表明分层测试产生算法能大大压缩电路测试集(约为66 ) ,而故障覆盖率有略微下降,时间性能也有些许降低。
" i use jtest for coding standards , unit test generation , test coverage , and both static and dynamic analysis . the new version is even more automated and i plan to use the team interface to share results with other developers and testers on my team . 用于编码标准、单元测试生成、测试覆盖,以及静态和动态分析。新的版本更加自动化,我打算利用小组接口于小组中其他的开发人员和测试人员共享结果。 ”
Three different d - fronts are defined in this paper , and the test generation is consisted of three parts : to excite the fault at first ; to maximize the iddt difference between fault - free circuit and faulty circuit at second ; and finally to minimize the effect of bypass 文中定义了三种不同的d前沿,并将测试生成分为三个部分: 1 、激活故障, 2 、使无故障电路和故障电路的瞬态电流差别最大化, 3 、减少旁路的影响。
Based on the analysis and research on fan algorithm , an iddt test pattern generation algorithm for stuck - open faults is present . in the case of ignoring hazards , for the stuck - open faults in cmos circuits , the feasibility of transient current test generation based on fan algorithm is discussed 本文采用启发式搜索的方法,基于对fan算法的分析,在不考虑冒险的情况下对于cmos电路中的开路故障,探讨了利用fan算法进行瞬态电流测试生成的可能性。
The design of complex and high - speed chips requires novel theories and approaches in design automation . boolean process theory is recently proposed to meet this requirement . based on boolean process , some theoretical extensions are made and novel techniques in design automation such as timing , test generation and basic research on verification and synthesis are proposed in this paper 布尔过程论是适应这种要求而提出的新的理论,本文以布尔过程论为理论基础,对该理论进行了拓展,探讨了该理论在复杂高速芯片设计自动化中的应用,在芯片定时、测试生成、验证和综合基础研究方面提出了几个基于该理论的自动化设计的新方法和新算法。