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- 算术单位
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- 算术运算器
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- 运算器运算部件
- 运算元素
- 运算装置
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arithmetic unit中文什么意思
例句与用法
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- 2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path
我们采用90纳米cmos标准单元工艺以及synopsys自动布局布线流程进行实验，实验结果表明该算法在高性能双通路结构的浮点加减运算中引入后，可以使得近路径的运算延迟整体降低10 . 2 % ，且算法本身没有造成新的关键路径。 - So , we must design multimedia application - oriented computer architecture to fit the data processing demand of video compressing programs , we analyzed the parallelism of two representative video compressing programs - opendivx and tml9 , and drew a conclusion that it is effective to run video compressing application programs on the processor which uses parallel arithmetic units
相对于视频压缩应用而言，普通计算机的处理能力大大落后于处理需求。因此，对于多媒体应用，必须采用并行的方法来解决，但是不能简单地使用普通并行机，必须针对这部分应用的特点，采用并行的思想来设计面向多媒体应用的计算机体系结构。 - With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ) , which conunon1y is composed of mcu , specified function ip cores , memory , periphery interface etc , the ip reuse techno1ogy is very important in s0c design flow , which can realize the constructions of different levels components . the approach of configurable system , method and design f1ow for udsm ( u1tra deep sub micron ) asic , logic system design using hdl 1anguage , coding style , static and dynamic verification strategy are a1so presented in chapter 2 . in chapter 3 we study the vlsi - - dsp architecture design , dense computation and high speed high performance digital signal processing unit structure , which includes high speed mac components and distributed arithmetic unit
在工程设计方法及结构化设计和高层次综合的研究中，介绍了在深亚微米工艺条件使用的方法和asic设计流程，讨论了高层次综合的核心如何从描述推出电路构成的设计思路，针对不同目标的设计技巧讨论了采用hdl语言进行逻辑系统设计的方法，给出了用vhdl语言进行代码设计时的规范和风格，在面向soc的验证策略讨论了动态和静态的验证技术，提出了进行单独模块验证、芯片的全功能验证和系统软硬件协同验证的整体策略。 - After that , it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler . moreover , this paper explores the method of design the floating - point arithmetic unit . referring to the ieee754 - 1985 standard for binary floating - point arithmetic , the algorithm and the behavior description of floating - point adder and multiplier is given , and the simulation and verification is shown at the end of this paper
此外，本文还对处理器的浮点运算单元设计做了初步的研究，以ansi ieee - 754浮点数二进制标准为参考，借鉴了经典的定点加法器和乘法器的设计，尝试性的给出了浮点加法单元和乘法单元的实现模型和行为级上的硬件描述，并对其进行仿真和验证。